Charge coupled devices (CCDs) that are used as image sensors are typically formed in lightly doped silicon materials. Light incident on the device and penetrating into the silicon produces electrons and holes in numbers proportional to the incident light intensity. The photogenerated electrons, having a higher mobility than the holes, are the preferred carrier to be collected and detected in such devices. These photogenerated electrons are transported in channels formed in lightly doped p-type silicon. Both, so-called, frame-transfer and interline transfer type CCD image sensing devices are typically fabricated in such lightly doped silicon. In interline transfer type devices and in some types of frame transfer type devices this is a lightly doped and relatively deeply diffused p-type region on an n-type silicon substrate. We will refer to such deeply diffused p-type regions as a p-well. Other types of frame transfer type devices may be fabricated in lightly doped p-type epitaxial silicon layers. Additional p-type dopant can be placed within surface regions of the silicon to form barriers and channel stops. These barriers and channel stops operate to confine signal charge within the CCD shift register (channel stops), in interline transfer type devices they can confine charge within the photodiode regions (barriers) and also separate individual phases of the CCD (barriers). The p-type doping used in these channel stop regions can provide a conductance path for movement of holes in and out of the active areas of the device. The conductance of these channel stops, however, is relatively low and, in certain circumstances, additional means are required to provide needed conductivity for the movement of the holes. An example of one means is described in U.S. Pat. No. 5,151,380, where a contact is formed and a metal conductor is added to provide sufficient conductance. One situation which can require a rapid and long distance movement of holes is in the, so-called, accumulation mode clocking of the CCD shift registers as will be described in the paragraphs below. Therefore, a shortcoming in the prior art exists in that there is a need for such added conductors to provide for conductance of hole charge in CCD image sensing devices operating in this mode of clocking.
For CCD image sensors in general, it is desirable to reduce the generation and collection of thermally generated charge produced either in photodiode regions or in the shift register regions of the device. The rate of production of such thermally generated charge is referred to as dark current. Dark current is undesirable because the thermally generated charge cannot be easily distinguished from the signal charges produced by light exposure. A common approach to reduce the dark current generated in the photodiode regions in interline transfer devices is to provide a surface p-type region with an accumulation of holes. Similarly, to reduce the dark current emanating from the CCD shift register surface regions, it is also desirable to maintain an accumulation of holes at the silicon surface. A four phase full frame type CCD device and clock sequence which accomplishes this has been described in U.S. Pat. No. 4,963,952, where a significant reduction in dark current generated under the CCD gates was observed when holes were accumulated beneath all gates. A gate which is biased in such a way to maintain the accumulation of holes at the silicon surface, is said to be in accumulation. A gate which is biased so that holes are not present is said to be in depletion.
Commonly-assigned U.S. Pat. No. 5,115,458, discloses additional invention related specifically to clocking techniques to reduce dark current in, so called, true two phase CCDs with a frame transfer architecture. By their description, true two phase CCD shift registers are those wherein each of the gate electrodes consist of a single conductive element with a storage and barrier region provided within the charge transfer channel. Description of such true two phase CCD shift registers as applied to interline transfer architecture has been disclosed in commonly-assigned U.S. Pat. Nos. 4,908,518 and 5,235,198. While the illustrations in this invention depict primarily such true two phase CCD shift registers, it should be clear that the invention also applies to other embodiments of two phase CCDs. Some examples of such embodiments, but not all such embodiments, may be found in references such as C. H. Sequin and M. F. Tompsett, Charge Transfer Devices, Academic Press, N.Y. 1975, pgs. 32–42.
CCD area arrays are typically arranged as rows and columns of light sensing elements, or pixels. In the typical operation of such a CCD image sensor array, charge is transferred row-by-row through a set of vertical shift registers, into a horizontal shift register, then the charges are transferred by the horizontal shift register to a detection circuit. The time during which a row of charges is transferred through the horizontal shift register is called the horizontal read-out time. During this time the vertical shift register CCD gates are held at some set of constant voltages. The vertical CCD gate voltages are clocked only during the brief period of time required to transfer a row of charge into the horizontal register, and are quiescent otherwise. This period of quiescence constitutes a majority of the time of operation of the device. It is during this period of quiescence that dark current problems arise in the vertical shift registers.
A true two phase CCD refers to a device in which there are two physical gates per pixel, with each gate having both a transfer and a storage region formed in the silicon under it. There are two voltage phase lines Φ1 and Φ2. The charge coupling concept is used in frame transfer and interline transfer CCD image sensing devices. An example of a frame transfer area image sensor 10 is shown in FIG. 1. Indicated, schematically, in FIG. 1a are the components of such a device, namely: a vertical shift register array, 40, arranged with rows and columns of pixels; channel stop regions 20, arranged to provide vertical channels 12; vertical gate electrodes 15 and 25; a horizontal shift register region 30, with gates 31 and 32; and, output amplifier 35. Electrical connections, to channel stop region 20, vertical gates 15 and 25 and horizontal gates 31 and 32, are also indicated. A schematic cross-section for a true two phase CCD is shown in FIG. 1b. A true two phase CCD is described in detail in commonly assigned U.S. Pat. No. 4,613,402. A true two phase CCD has storage and transfer regions beneath each phase gate. In FIG. 1b the phase gates are labeled by 101 and 106, and are situated above a silicon substrate 100 and isolated from the substrate by an insulating layer 103. The transfer and storage regions for these gates are indicated, respectively, as regions 102 and 104 for gates 101(Φ1), and 107 and 108 for gates 106 (Φ2). In this drawing, additional dopants are indicated to be present in regions 102 and 107 in order to provide a suitable potential energy profile for efficient transfer of charge in the CCD register. These dopants are in addition to other dopants commonly introduced to provide, for example, a buried channel, for transport of signal charges. In FIG. 1c, the potential energy profile in the channel beneath the gates is indicated for the condition that voltage Φ2 is more positive than the voltage Φ1. For this voltage condition charge packets 201 and 202 reside in the storage regions 108 beneath the respective Φ2 gates. The dopants in regions 102 and 107 produce the potential energy steps 205 and 206 which provide the directionality for charge transfer.
In this disclosure only n-buried channel devices will be considered. This invention applies equally to p-buried channel devices. For an n channel CCD, which is illustrated, the buried channel is formed by an n-type doping in a p-type substrate or in a p-well in an n-type substrate. The transfer and storage buried channel regions are differentiated by less or more of the n-buried channel doping, respectively. Commonly-assigned U.S. Pat. No. 4,613,402 discloses a detailed procedure for making true two phase CCD devices. In a buried channel CCD, dark current arises from three main sources: (1) generation from a midgap state resulting from either the disrupted lattice or an impurity at a depleted Si—SiO2 interface, (2) generation in the depletion region, that is, a region depleted of mobile charge, as a result of an impurity or defect with a midgap state and (3) diffusion of electrons to the buried channel from the substrate. All three sources, result in spurious charges being collected as signal in the buried channel. The mechanism for dark current generation both at the surface and in the depletion region has been described in commonly-assigned U.S. Pat. No. 5,115,458. It is an object of this invention to reduce the surface state component of dark current.
A clocking sequence which accomplishes such an accumulation of surface holes at all gates of the vertical shift register for a majority of the time, is called, accumulation mode clocking. One such clocking sequence for the vertical shift register of a two-phase CCD device is diagrammed in FIG. 2. In the first part of this figure, FIG. 2a, the clock voltages which are applied to first phase, Φ1, and second phase, Φ2, are diagrammed as a function of time. Time intervals, to through t3, designate the various parts of this clock sequence. The charge transfer process resulting from the clocking diagrammed in FIG. 2a is shown schematically in FIG. 2b, where, for the various time periods indicated in FIG. 2a, the potential energy, and the location of signal electrons, are schematically indicated. In FIG. 2b, the vertical direction represents the potential energy of electrons and the horizontal direction representing distance along the CCD shift register. In FIG. 2b, the gate pair, Φ2 and Φ1 on the left, define a first pixel position and the gate pair Φ2 and Φ1, on the right define a second pixel position. In FIG. 2b, the signal charges, denoted by the circular objects, and the hole charges, denoted by the + signs, are diagrammed at times t0 through t3. Also, in this figure, the barrier region channel potential under the Φ1 gate is taken to be higher (i.e. a lower potential energy barrier) than the channel potential under the barrier region of the Φ2 gate. This situation is similar to that described in commonly-assigned U.S. Pat. No. 5,235,198 and the clocking was termed, by them, as a “spill backward” mode. The reason for this terminology will be indicated below.
As represented in FIG. 2b, the positive clock voltage transitions produce deeper potential energy regions for electrons and higher potential energy regions for holes. Conversely, the more negative clock voltages produce lower potential energy regions for holes and higher potential energy regions for electrons. This clocking sequence is equivalent to that shown in FIG. 5 of commonly-assigned U.S. Pat. No. 5,115,458. Note that for this example, the barrier region electron's potential energy on the left side of the Φ1 gate is lower than the potential energy of the barrier region on the left side of the Φ2 gate. The upshot of this potential energy difference is that, during the period when both gates are in accumulation, signal charge may be stored beneath either or both of the CCD gates. This particular mode of operation is called the “spill backward mode” because any signal charge in excess of what can be accommodated under the Φ1 accumulated gate, is spilled backwards, in this case to the Φ2 gate, when the clocks return to the hole accumulated state at time t3.
In this illustration, it should be noted that the total hole charge under the gate pairs of each pixel, during each successive interval of the clocking, does not remain constant. For example, when both gates are biased negative (−9 volts is chosen as an example) an amount of holes, Q, is accumulated under each gate, and, thus, the total charge under the pair of gates is 2Q. The hole charge, q, under each gate, during each interval of time, is also indicated in the timing diagram FIG. 2a. When one gate is brought more positive, for example, to 0 volts in this illustration, the total hole charge is reduced to only 1Q. The excess hole charge, an amount Q per pixel, must be removed in some way. It is evident that approximately half of the total accumulated hole charge for each pixel must be removed in the transitions between times t0 and t1, and then replaced between t3a and t3, respectively.
The typical path for such hole charge removal or replacement is via a p-doped region such as the channel stop. For large devices, the net charge that must be moved in this way is significantly impeded by the relatively high resistance of the p-type regions. While this is true for any CCD operating in accumulation mode, this is a particularly troublesome problem for devices which are fabricated in deeply diffused p-doped regions on an n-type substrate. The problem becomes more severe as the area of the devices are made larger. This deeply diffused p-type region, referred to as a p-well, is typically isolated or only weakly connected with surface p-regions such as channel stops. The total amount of charge which must be drained off during the time one of the gates is in depletion is nQ, where n is the total number of pixels in the image sensor. During the time required to drain off the excess hole charge, the local value of the p-well bias moves, particularly in the central regions of the device, creating an undesirable biasing which leads to poor imaging properties for the device. This undesirable potential variation is sometimes referred to as p-well bounce. There is, thus, a shortcoming within the prior art in avoiding p-well bounce when attempting to employ accumulation mode clocking.
It should be readily apparent that there remains a need within the art for a method and apparatus that can be used to clock image sensing devices in accumulation mode that does not result in dark current signal in interline transfer type CCD image sensors. In particular, it should be apparent that there is a need within the art for a method of operation of interline CCD devices with reduced dark current and which also avoids the need to transport hole charge by large distances. Prior art devices, as previously discussed, have a problem in not providing a suitable clocking sequence which results in lowered dark current signals in large area devices, and in particular in interline transfer type CCD image sensors.